Magnetoresistive Random Access Memory (MRAM), based on the integration of silicon CMOS with magnetic tunnel junction (MTJ) technology, is a strong candidate to provide a dense (8-25F2 cell size), fast (1˜30 ns read/write speed), and non-volatile storage solution for future memory applications. The MTJ utilizes a thin dielectric insulating layer like AlOx, AlNxOy, or MgOx that is formed between a first ferromagnetic layer which is pinned in a certain direction by an adjacent anti-ferromagnetic (AFM) layer, and a second ferromagnetic (free) layer. The pinned layer has a magnetic moment that is fixed in the “y” direction, for example, by exchange coupling with the adjacent AFM layer that is also magnetized in the “y” direction. The free layer has a magnetic moment that is either parallel or anti-parallel to the magnetic moment in the pinned layer. The tunnel barrier layer is thin enough that a current through it can be established by quantum mechanical tunneling of conduction electrons. The magnetic moment of the free layer may change in response to external magnetic fields and it is the relative orientation of the magnetic moments between the free and pinned layers that determines the tunneling current and therefore the resistance of the tunneling junction. When a sense current is passed from the top electrode to the bottom electrode in a direction perpendicular to the MTJ layers, a lower resistance is detected when the magnetization directions of the free and pinned layers are in a parallel state (“1” memory state) and a higher resistance is noted when they are in an anti-parallel state or “0” memory state.
A MRAM device is generally comprised of an array of parallel first conductive lines on a horizontal plane, an array of parallel second conductive lines on a second horizontal plane spaced above and formed in a direction perpendicular to the first conductive lines, and a MTJ cell interposed between a first conductive line (i.e. word line) and a second conductive line (i.e. bit line) at each crossover location. In a read operation, the information stored in a MRAM is read by sensing the magnetic state (resistance level) of the MTJ cell through a sense current flowing top to bottom through the cell in a current perpendicular to plane (CPP) configuration. During a write operation, information is written to the MRAM by changing the magnetic state in the free layer to an appropriate one by generating external magnetic fields as a result of applying bit line and word line currents in two crossing conductive lines, either above or below the MTJ cell. Thus, the cross point of word line and bit line currents is used to program a MTJ cell. In FIG. 1a, a switching field asteroid is depicted for a conventional MRAM and in FIG. 1b, a bit line 1 is shown crossing over a MTJ cell 3 and a word line 2 that is below the MTJ cell.
The problem of MTJ cells being disturbed along the same word line and bit lines is a major concern. Switching fields generated by word line and bit line currents for the conventional MRAM are about 30 to 60 Oe in intensity. The MRAM has to generate a relatively large electric current magnetic field to rewrite recorded information. Hence, an electric current of a certain large magnitude should flow through the address wirings in order to produce a sufficient magnetic field for the write process.
As memory devices are increasingly micro-miniaturized, the address wiring is also reduced in width so that it becomes difficult to apply a sufficient electric current to the address wiring. Additionally, coercive force of the device is increased thereby leading to a greater electric current magnetic field and a higher power consumption in the device. For this reason, a memory structure that employs magnetization switching driven by a spin transfer mechanism is receiving more attention as a configuration capable of switching the magnetization direction by application of a small electric current.
Spin transfer (spin torque) magnetization switching is described in detail by J. Slonczewski in U.S. Pat. No. 5,695,864 and by Redon et al. in U.S. Pat. No. 6,532,164. The spin-transfer effect arises from the spin dependent electron transport properties of ferromagnetic-spacer-ferromagnetic multilayers. When a spin-polarized current transverses a magnetic multilayer in a CPP configuration, the spin angular moment of electrons incident on a ferromagnetic layer interacts with magnetic moments of the ferromagnetic layer near the interface between the ferromagnetic and non-magnetic spacer. Through this interaction, the electrons transfer a portion of their angular momentum to the ferromagnetic layer. For example, when spin-polarized electrons are passed through a magnetic layer having a particular magnetic moment in a preferred easy axis direction, these spin-polarized electrons will cause a continuous rotation of the magnetic moment vector which may result in a reversal of the magnetic moment vector along its easy axis. Thus, switching the magnetic moment vector between its two preferred directions along the easy axis may be effected by passing spin-polarized electrons perpendicularly through the magnetic layer. The difference between a Spin-RAM and a conventional MRAM is only in the write operation mechanism. The read mechanism is the same.
Recent experimental data from W. Rippard et al. in Phys. Rev. Left., 92, p. 027201[3] (2004) confirms the very essence of magnetic moment transfer as a source of magnetic excitations, and subsequently, switching. These experiments also confirm theoretical predictions by J. Slonczewski in “Current-driven excitation of magnetic multilayers”, J. Magn. Magn. Materials V 159, L1-L7 (1996), and by J. Sun in Phys Rev. B, Vol. 62, p. 570[5] (2000), stating that the spin-transfer generated net torque term (Γ) acting on the magnetization under conditions of spin-polarized DC current is expressed by the equation: Γ=s nm×(ns×nm) where s is the spin-angular momentum deposition rate, ns is a unit vector whose direction is that of the initial spin direction of the current, and nm is a unit vector whose direction is that of the free layer magnetization. The above equation indicates that the torque will have a maximum value when ns is orthogonal to nm.
Referring to FIG. 2, a prior art spin-transfer MRAM, also referred to as a Spin-RAM, is depicted from a cross-sectional view. The storage element (MTJ) 10 is formed between a bottom electrode 16 and a top electrode (bit line) 25 and is comprised of an underlayer 17, an AFM layer 18, synthetic anti-ferromagnetic (SyAF) reference layer made of layers 19-21, a tunnel barrier layer 22, a free storage layer 23, and a capping layer 24. The bottom electrode 16 is connected to a CMOS transistor having a source 12, drain 13, and p-type semiconductor substrate 11 that provides current for switching the MTJ free layer 23. For data writing, as a current flowing across the storage element from bottom to top reaches a critical current, the magnetization of the free layer 23 will be written to be anti-parallel to the magnetization direction of the reference layer (i.e. a high resistance state). As a current flowing across the storage element from top to bottom reaches a critical current, the magnetization of the free layer 23 will be written to be parallel to that of the reference layer (i.e. a low resistance state). During the read process, a small current flows across the MTJ cell and its resistance is compared with a pre-written MTJ cell (called a reference cell) to determine whether it is in a high resistance state or low resistance state. Typically, the read margin is determined by the ratio between the magnetoresistive ratio (dR/R), and the coefficient of resistance variance (σ/μ) which is the ratio between the resistance standard deviation σ and the resistance mean value μ.
A critical current for spin transfer switching (Ic), which is defined as [(Ic++I Ic− I)/2], for the present 180 nm node sub-micron MTJ having a top-down area of about 0.2×0.4 micron, is generally a few milliamperes. The critical current density (Jc), for example (Ic/A), is on the order of several 107 A/cm2. This high current density, which is required to induce the spin-transfer effect, could destroy a thin tunnel barrier layer such as AlOx, MgO, or the like. In order for spin-transfer magnetization switching to be viable in the 90 nm technology node and beyond, the critical current density (Jc) must be lower than 106 A/cm2 to be driven by a CMOS transistor that can typically deliver 100 μA per 100 nm gate width. For Spin-RAM applications, the (ultra-small) MTJs must exhibit a high tunnel magnetoresistance ratio (TMR or dR/R) much higher than the conventional MRAM-MTJ that use AlOx as a barrier layer. To apply spin-transfer switching to MRAM technology, it is desirable to decrease Ic (and its Jc) by more than an order of magnitude so as to avoid an electrical breakdown of the MTJ device and to be compatible with the underlying CMOS transistor that is used to provide switching current and to select a memory cell.
Normally, the write current density required to switch free layer magnetization is mainly determined by the MTJ free layer magnetization moment, damping ratio, and spin-angular momentum deposition rate which depends on the type and quality of the materials used in the MTJ stack of layers. As the device is micro-miniaturized to nanometer scale dimensions, the write current density is unchanged, giving a much smaller write current which is scalable to the shrinking MTJ dimensions. Hence, power consumption of the device is reduced. Since write current also flows across the MTJ tunnel barrier layer, the reliability of MTJ cells becomes a large problem due to the fact that the MTJ will be damaged as the voltage across a MTJ junction reaches a threshold, the so-called breakdown voltage. In order to solve this problem, a new design has been proposed in U.S. Pat. No. 7,149,106 that is illustrated in FIG. 3. During the write process, a magnetic field from a digit line 31 rotates the magnetization in a polarizer 39 toward one direction which the magnetization of the free layer 37 is written to, and an electric current 41 flows only from one section 40a of the write line across the polarizer 39 and returns to a second section 40b of the write line through a conducting spacer 38. The write current 41 generates a spin-transfer interaction between the magnetic polarizer 39 and free layer 37 thereby causing a switch in free layer magnetization. The MTJ cell 30 is also comprised of an AFM/bottom electrode 32, AP2 layer 33, Ru coupling layer 34, AP1 layer 35, and a tunnel barrier layer 36.
Since the write current does not directly flow into the free layer in this design, only a very small surface portion of the free layer magnetization may experience a spin-transfer effect. Moreover, the conducting spacer must be made very thin in order to deliver polarized spin current to free layer magnetization more efficiently. Even so, the spin-transfer effect could still be very small. Thus, a large write current would be required. Additionally, a thin conducting spacer is very difficult to fabricate and a high current density flowing along the spacer layer would likely cause a reliability problem.
Therefore, an improved design is needed for a Spin-RAM that avoids an operating voltage which could damage the MTJ tunnel barrier while providing a low write current, and high dR/R. Also, as the MRAM dimension shrinks, it is becoming increasingly difficult during a read process to differentiate between a “0” and a “1” state when comparing the resistance in the MTJ cell to a reference cell in the periphery of the circuit. Ideally, a better method is needed that does not rely on a reference cell outside the bit so that the reliability of the read process is improved and the “read” time is minimized.
A routine search of the prior art was conducted and the following references were found. U.S. Pat. No. 7,173,848 discloses a stack of two memory cells separated by a non-magnetic layer. In related U.S. Patent Application No. 2006/0202244, there are memory stacks in an X-Y plane where each stack has two memory cells stacked along a Z-axis direction.
U.S. Pat. No. 5,930,164 shows a stack of two memory cells where the bottom cell is larger and the two cells are separated by a conductive layer made of Cu.
In U.S. Pat. No. 6,927,948, two differential CPP cells are stacked together and are separated by a metal gap layer.
U.S. Patent Application 2006/0146597 discloses a security device comprising two paired MRAM cells.
U.S. Pat. No. 7,095,648 describes a matrix of memory cells arranged in rows and columns where one cell in a column (or row) is read while another cell in the same column (or row) is written simultaneously.
U.S. Pat. No. 7,009,877 discloses a magnetic memory device having three terminals in which a spin transfer (ST) driven element is formed between a first terminal and a second terminal, and a MTJ element is disposed between the second terminal and a third terminal. Magnetization reversal of a first free layer within the ST element causes the magnetization direction in a second free layer within the MTJ to switch and thereby records a data state. However, this reference does not teach how the interaction between the two free layers can be optimized to improve switching efficiency. Moreover, the memory device relies on a reference cell outside the bit cell during the read process which can slow the device speed.
U.S. Pat. No. 7,230,844 states that a thermal factor represented by KUMSV/kBT where KU is the anisotropy constant, Ms is the saturation magnetization, V is the volume of the FM2 free layer, kB is the Boltzmann constant, and T is the temperature, should be greater than 40 to assure a minimum length for data retention of 10 years in a magnetic material memory element.